projects / ds1820tousb.git / blame
| Commit | Line | Data |
|---|---|---|
| 93ac315e MPM |
1 | /* Name: oddebug.h |
| 2 | * Project: AVR library | |
| 3 | * Author: Christian Starkjohann | |
| 4 | * Creation Date: 2005-01-16 | |
| 5 | * Tabsize: 4 | |
| 6 | * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH | |
| 7 | * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) | |
| 8 | * This Revision: $Id: oddebug.h 692 2008-11-07 15:07:40Z cs $ | |
| 9 | */ | |
| 10 | ||
| 11 | #ifndef __oddebug_h_included__ | |
| 12 | #define __oddebug_h_included__ | |
| 13 | ||
| 14 | /* | |
| 15 | General Description: | |
| 16 | This module implements a function for debug logs on the serial line of the | |
| 17 | AVR microcontroller. Debugging can be configured with the define | |
| 18 | 'DEBUG_LEVEL'. If this macro is not defined or defined to 0, all debugging | |
| 19 | calls are no-ops. If it is 1, DBG1 logs will appear, but not DBG2. If it is | |
| 20 | 2, DBG1 and DBG2 logs will be printed. | |
| 21 | ||
| 22 | A debug log consists of a label ('prefix') to indicate which debug log created | |
| 23 | the output and a memory block to dump in hex ('data' and 'len'). | |
| 24 | */ | |
| 25 | ||
| 26 | ||
| 27 | #ifndef F_CPU | |
| 28 | # define F_CPU 12000000 /* 12 MHz */ | |
| 29 | #endif | |
| 30 | ||
| 31 | /* make sure we have the UART defines: */ | |
| 32 | #include "usbportability.h" | |
| 33 | ||
| 34 | #ifndef uchar | |
| 35 | # define uchar unsigned char | |
| 36 | #endif | |
| 37 | ||
| 38 | #if DEBUG_LEVEL > 0 && !(defined TXEN || defined TXEN0) /* no UART in device */ | |
| 39 | # warning "Debugging disabled because device has no UART" | |
| 40 | # undef DEBUG_LEVEL | |
| 41 | #endif | |
| 42 | ||
| 43 | #ifndef DEBUG_LEVEL | |
| 44 | # define DEBUG_LEVEL 0 | |
| 45 | #endif | |
| 46 | ||
| 47 | /* ------------------------------------------------------------------------- */ | |
| 48 | ||
| 49 | #if DEBUG_LEVEL > 0 | |
| 50 | # define DBG1(prefix, data, len) odDebug(prefix, data, len) | |
| 51 | #else | |
| 52 | # define DBG1(prefix, data, len) | |
| 53 | #endif | |
| 54 | ||
| 55 | #if DEBUG_LEVEL > 1 | |
| 56 | # define DBG2(prefix, data, len) odDebug(prefix, data, len) | |
| 57 | #else | |
| 58 | # define DBG2(prefix, data, len) | |
| 59 | #endif | |
| 60 | ||
| 61 | /* ------------------------------------------------------------------------- */ | |
| 62 | ||
| 63 | #if DEBUG_LEVEL > 0 | |
| 64 | extern void odDebug(uchar prefix, uchar *data, uchar len); | |
| 65 | ||
| 66 | /* Try to find our control registers; ATMEL likes to rename these */ | |
| 67 | ||
| 68 | #if defined UBRR | |
| 69 | # define ODDBG_UBRR UBRR | |
| 70 | #elif defined UBRRL | |
| 71 | # define ODDBG_UBRR UBRRL | |
| 72 | #elif defined UBRR0 | |
| 73 | # define ODDBG_UBRR UBRR0 | |
| 74 | #elif defined UBRR0L | |
| 75 | # define ODDBG_UBRR UBRR0L | |
| 76 | #endif | |
| 77 | ||
| 78 | #if defined UCR | |
| 79 | # define ODDBG_UCR UCR | |
| 80 | #elif defined UCSRB | |
| 81 | # define ODDBG_UCR UCSRB | |
| 82 | #elif defined UCSR0B | |
| 83 | # define ODDBG_UCR UCSR0B | |
| 84 | #endif | |
| 85 | ||
| 86 | #if defined TXEN | |
| 87 | # define ODDBG_TXEN TXEN | |
| 88 | #else | |
| 89 | # define ODDBG_TXEN TXEN0 | |
| 90 | #endif | |
| 91 | ||
| 92 | #if defined USR | |
| 93 | # define ODDBG_USR USR | |
| 94 | #elif defined UCSRA | |
| 95 | # define ODDBG_USR UCSRA | |
| 96 | #elif defined UCSR0A | |
| 97 | # define ODDBG_USR UCSR0A | |
| 98 | #endif | |
| 99 | ||
| 100 | #if defined UDRE | |
| 101 | # define ODDBG_UDRE UDRE | |
| 102 | #else | |
| 103 | # define ODDBG_UDRE UDRE0 | |
| 104 | #endif | |
| 105 | ||
| 106 | #if defined UDR | |
| 107 | # define ODDBG_UDR UDR | |
| 108 | #elif defined UDR0 | |
| 109 | # define ODDBG_UDR UDR0 | |
| 110 | #endif | |
| 111 | ||
| 112 | static inline void odDebugInit(void) | |
| 113 | { | |
| 114 | ODDBG_UCR |= (1<<ODDBG_TXEN); | |
| 115 | ODDBG_UBRR = F_CPU / (19200 * 16L) - 1; | |
| 116 | } | |
| 117 | #else | |
| 118 | # define odDebugInit() | |
| 119 | #endif | |
| 120 | ||
| 121 | /* ------------------------------------------------------------------------- */ | |
| 122 | ||
| 123 | #endif /* __oddebug_h_included__ */ |