add citation information

[LbmBenchmarkKernelsPublic.git] / doc / main.html

diff --git a/doc/main.html b/doc/main.html
index dfd45ecc93a1b4bea8ec14e1fd029069ba807551..c5f822360e52fda01023e2a0ff6c43b7e56f80e4 100644 (file)
--- a/doc/main.html
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@@ -592,7 +592,7 @@ make clean-all
 <tr><td>OPENMP</td>
 <td>on, off</td>
 <td>on</td>
-<td>OpenMP, i.,e.. threading support.</td>
+<td>OpenMP, i.e. threading support.</td>
 </tr>
 <tr><td>PRECISION</td>
 <td>dp, sp</td>
@@ -637,6 +637,22 @@ make clean-all
 </tr>
 </thead>
 <tbody valign="top">
+<tr><td>ADJ_LIST_MEM_TYPE</td>
+<td>HBM</td>
+<td><ul class="first last simple">
+<li></li>
+</ul>
+</td>
+<td>Determines memory location of adjacency list array, DRAM or HBM.</td>
+</tr>
+<tr><td>PDF_MEM_TYPE</td>
+<td>HBM</td>
+<td><ul class="first last simple">
+<li></li>
+</ul>
+</td>
+<td>Determines memory location of PDF array, DRAM or HBM.</td>
+</tr>
 <tr><td>SOFTWARE_PREFETCH_LOOKAHEAD_L1</td>
 <td>int &gt;= 0</td>
 <td>0</td>
@@ -1153,7 +1169,6 @@ which mimics the kernels memory access pattern and the kernel's loop balance
 </li>
 </ul>
 <p><strong>Skylake, Intel Xeon Gold 6148</strong></p>
-<p>NOTE: currently we only use AVX2 intrinsics.</p>
 <ul class="simple">
 <li>Skylake server architecture, AVX2, AVX512, 2 FMA units</li>
 <li>20 cores, 2.4 GHz</li>
@@ -1225,11 +1240,11 @@ which mimics the kernels memory access pattern and the kernel's loop balance
 </tr>
 <tr><td><img alt="perf_meggie_sp" src="images/benchmark-meggie-sp.png" style="width: 1000.0px; height: 250.0px;" /></td>
 </tr>
-<tr><td>Skylake, Intel Xeon Gold 6148, Double Precision, <strong>NOTE: currently we only use AVX2 intrinsics.</strong></td>
+<tr><td>Skylake, Intel Xeon Gold 6148, Double Precision</td>
 </tr>
 <tr><td><img alt="perf_skylakesp2_dp" src="images/benchmark-skylakesp2-dp.png" style="width: 1000.0px; height: 250.0px;" /></td>
 </tr>
-<tr><td>Skylake, Intel Xeon Gold 6148, Single Precision, <strong>NOTE: currently we only use AVX2 intrinsics.</strong></td>
+<tr><td>Skylake, Intel Xeon Gold 6148, Single Precision</td>
 </tr>
 <tr><td><img alt="perf_skylakesp2_sp" src="images/benchmark-skylakesp2-sp.png" style="width: 1000.0px; height: 250.0px;" /></td>
 </tr>
@@ -1259,6 +1274,21 @@ which mimics the kernels memory access pattern and the kernel's loop balance
 </div>
 <div class="section" id="acknowledgements">
 <h1><a class="toc-backref" href="#id27">8&nbsp;&nbsp;&nbsp;Acknowledgements</a></h1>
+<p>If you use the benchmark kernels you can cite us:</p>
+<p>M. Wittmann, V. Haag, T. Zeiser, H. Köstler, and G. Wellein: Lattice Boltzmann
+Benchmark Kernels as a Testbed for Performance Analysis, (2018), Computer &amp;
+Fluids, Special Issue DSFD2017. doi:10.1016/j.compfluid.2018.03.030.</p>
+<p>Bibtex entry:</p>
+<pre class="literal-block">
+&#64;article{wittmann-2018,
+    author  = {M. Wittmann and V. Haag and T. Zeiser and H. K\&quot;ostler and G. Wellein},
+    title   = {Lattice {B}oltzmann benchmark kernels as a testbed for performance analysis},
+    journal = {Computers \&amp; Fluids},
+    year    = {2018},
+    issn    = {0045-7930},
+    doi     = {10.1016/j.compfluid.2018.03.030},
+}
+</pre>
 <p>This work was funded by BMBF, grant no. 01IH15003A (project SKAMPY).</p>
 <p>This work was funded by KONWHIR project OMI4PAPS.</p>
 </div>
@@ -1280,7 +1310,7 @@ Roofline: an insightful visual performance model for multicore architectures.
 Commun. ACM, 52(4):65-76, Apr 2009. doi:10.1145/1498765.1498785</td></tr>
 </tbody>
 </table>
-<p>Document was generated at 2018-05-10 14:10.</p>
+<p>Document was generated at 2018-06-06 10:38.</p>
 </div>
 </div>
 </body>