X-Git-Url: http://git.rrze.uni-erlangen.de/gitweb/?p=LbmBenchmarkKernelsPublic.git;a=blobdiff_plain;f=doc%2Fmain.html;fp=doc%2Fmain.html;h=dfd45ecc93a1b4bea8ec14e1fd029069ba807551;hp=9f1186603c5019c8cbf6dad1ad6594bffb7d4de0;hb=8cafd9ea08a6b1103eab29811227a7ae536dffa6;hpb=0fde6e45e9be83893afae896cf49a799777f6d7c
diff --git a/doc/main.html b/doc/main.html
index 9f11866..dfd45ec 100644
--- a/doc/main.html
+++ b/doc/main.html
@@ -401,6 +401,10 @@ tr:nth-child(odd) {
Viktor Haag, 2016
LSS, University of Erlangen-Nuremberg, Germany
+Michael Hussnaetter, 2017-2018
+University of Erlangen-Nuremberg, Germany
+michael.hussnaetter -at- fau.de
+
This file is part of the Lattice Boltzmann Benchmark Kernels (LbmBenchKernels).
@@ -581,7 +585,7 @@ make clean-all
Select GCC or Intel compiler. |
| ISA |
-avx, sse |
+avx512, avx, sse |
avx |
Determines which ISA extension is used for macro definitions of the intrinsics. This is not the architecture the compiler generates code for. |
@@ -617,6 +621,35 @@ make clean-all
+Suboptions for ``ISA=avx512``
+
+
+
+
+
+
+
+
+| name |
+values |
+default |
+description |
+
|---|
+
+
+| SOFTWARE_PREFETCH_LOOKAHEAD_L1 |
+int >= 0 |
+0 |
+Software prefetch lookahead of elements into L1 cache, value is multiplied by vector size (VSIZE). |
+
+| SOFTWARE_PREFETCH_LOOKAHEAD_L2 |
+int >= 0 |
+0 |
+Software prefetch lookahead of elements into L2 cache, value is multiplied by vector size (VSIZE). |
+
+
+
+Please note this options require AVX-512 PF support of the target processor.
@@ -637,7 +670,7 @@ LBM Benchmark Kernels 0.1, compiled Jul 5 2017 21:59:22, type: benchmark
Usage:
./lbmbenchk -list
./lbmbenchk
- [-dims XxYyZ] [-geometry box|channel|pipe|blocks[-<block size>]] [-iterations <iterations>] [-lattice-dump-ascii]
+ [-dims XxYxZ] [-geometry box|channel|pipe|blocks[-<block size>]] [-iterations <iterations>] [-lattice-dump-ascii]
[-rho-in <density>] [-rho-out <density] [-omega <omega>] [-kernel <kernel>]
[-periodic-x]
[-t <number of threads>]
@@ -952,13 +985,14 @@ created make sure the binary was compiled with:
- BENCHMARK=on (default if not overriden) and
- BUILD=release (default if not overriden) and
-- the correct ISA for macros is used, selected via ISA and
+- the correct ISA for macros (i.e. intrinsics) is used, selected via ISA and
- use TARCH to specify the architecture the compiler generates code for.
For the Intel compiler one can specify depending on the target ISA extension:
+- SSE: TARCH=-xSSE4.2
- AVX: TARCH=-xAVX
- AVX2 and FMA: TARCH=-xCORE-AVX2,-fma
- AVX512: TARCH=-xCORE-AVX512
@@ -974,12 +1008,26 @@ make ISA=avx TARCH=-xCORE-AVX2,-fma
WARNING: ISA is here still set to avx as currently we have the FMA intrinsics not
implemented. This might change in the future.
+
+
Compiling for an architecture supporting AVX-512 (Skylake):
-make ISA=avx TARCH=-xCORE-AVX512
+make ISA=avx512 TARCH=-xCORE-AVX512
+
+
Please note that for the AVX512 gather kernels software prefetching for the
+gather instructions is disabled per default.
+To enable it set SOFTWARE_PREFETCH_LOOKAHEAD_L1 and/or
+SOFTWARE_PREFETCH_LOOKAHEAD_L2 to a value greater than 0 during
+compilation. Note that this requires AVX-512 PF support from the target
+processor.
+
Compiling for MIC architecture KNL supporting AVX-512 and AVX-512 PF:
+
+make ISA=avx512 TARCH=-xMIC-AVX512
+
+
or optionally with software prefetch enabled:
+
+make ISA=avx512 TARCH=-xMIC-AVX512 SOFTWARE_PREFETCH_LOOKAHEAD_L1=<value> SOFTWARE_PREFETCH_LOOKAHEAD_L2=<value>
-
WARNING: ISA is here still set to avx as currently we have no implementation for the
-AVX512 intrinsics. This might change in the future.
@@ -1232,7 +1280,7 @@ Roofline: an insightful visual performance model for multicore architectures.
Commun. ACM, 52(4):65-76, Apr 2009. doi:10.1145/1498765.1498785
-
Document was generated at 2018-01-09 11:54.
+
Document was generated at 2018-05-10 14:10.