X-Git-Url: http://git.rrze.uni-erlangen.de/gitweb/?p=LbmBenchmarkKernelsPublic.git;a=blobdiff_plain;f=doc%2Fhtml%2Fmain.html;fp=doc%2Fhtml%2Fmain.html;h=0000000000000000000000000000000000000000;hp=99f4cb847eb50e75fbbfdbbf68c260645dd031ef;hb=0fde6e45e9be83893afae896cf49a799777f6d7c;hpb=712d0b8fc4a382e1cfe4edef8b0ade11b0a2ce25 diff --git a/doc/html/main.html b/doc/html/main.html deleted file mode 100644 index 99f4cb8..0000000 --- a/doc/html/main.html +++ /dev/null @@ -1,1910 +0,0 @@ - - - - - - -LBM Benchmark Kernels Documentation - - - - -
-

LBM Benchmark Kernels Documentation

- - -
-

Contents

- -
-
-

1   Introduction

-

The lattice Boltzmann (LBM) benchmark kernels are a collection of LBM kernel -implementations.

-

AS SUCH THE LBM BENCHMARK KERNELS ARE NO FULLY EQUIPPED CFD SOLVER AND SOLELY -SERVES THE PURPOSE OF STUDYING POSSIBLE PERFORMANCE OPTIMIZATIONS AND/OR -EXPERIMENTS.

-

Currently all kernels utilize a D3Q19 discretization and the -two-relaxation-time (TRT) collision operator [ginzburg-2008]. -All operations are carried out in double precision arithmetic.

-
-
-

2   Compilation

-

The benchmark framework currently supports only Linux systems and the GCC and -Intel compilers. Every other configuration probably requires adjustment inside -the code and the makefiles. Furthermore some code might be platform or at least -POSIX specific.

-

The benchmark can be build via make from the src subdirectory. This will -generate one binary which hosts all implemented benchmark kernels.

-

Binaries are located under the bin subdirectory and will have different names -depending on compiler and build configuration.

-

Compilation can target debug or release builds. Combined with both build types -verification can be enabled, which increases the runtime and hence is not -suited for benchmarking.

-
-

2.1   Debug and Verification

-
-make BUILD=debug BENCHMARK=off
-
-

Running make with BUILD=debug builds the debug version of -the benchmark kernels, where no optimizations are performed, line numbers and -debug symbols are included as well as DEBUG will be defined. The resulting -binary will be found in the bin subdirectory and named -lbmbenchk-linux-<compiler>-debug.

-

Specifying BENCHMARK=off turns on verification -(VERIFICATION=on), statistics (STATISTICS=on), and VTK output -(VTK_OUTPUT=on) enabled.

-

Please note that the generated binary will therefore -exhibit a poor performance.

-
-
-

2.2   Release and Verification

-

Verification with the debug builds can be extremely slow. Hence verification -capabilities can be build with release builds:

-
-make BENCHMARK=off
-
-
-
-

2.3   Benchmarking

-

To generate a binary for benchmarking run make with

-
-make
-
-

As default BENCHMARK=on and BUILD=release is set, where -BUILD=release turns optimizations on and BENCHMARK=on disables -verfification, statistics, and VTK output.

-

See Options Summary below for further description of options which can be -applied, e.g. TARCH as well as the Benchmarking section.

-
-
-

2.4   Compilers

-

Currently only the GCC and Intel compiler under Linux are supported. Between -both configuration can be chosen via CONFIG=linux-gcc or -CONFIG=linux-intel.

-
-
-

2.5   Cleaning

-

For each configuration and build (debug/release) a subdirectory under the -src/obj directory is created where the dependency and object files are -stored. -With

-
-make CONFIG=... BUILD=... clean
-
-

a specific combination is select and cleaned, whereas with

-
-make clean-all
-
-

all object and dependency files are deleted.

-
-
-

2.6   Options Summary

-

Options that can be specified when building the suite with make:

- ------ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
namevaluesdefaultdescription
BENCHMARKon, offonIf enabled, disables VERIFICATION, STATISTICS, VTK_OUTPUT. If disabled enables the three former options.
BUILDdebug, releasereleasedebug: no optimization, debug symbols, DEBUG defined. release: optimizations enabled.
CONFIGlinux-gcc, linux-intellinux-intelSelect GCC or Intel compiler.
ISAavx, sseavxDetermines which ISA extension is used for macro definitions of the intrinsics. This is not the architecture the compiler generates code for.
OPENMPon, offonOpenMP, i.,e.. threading support.
STATISTICSon, offoffView statistics, like density etc, during simulation.
TARCH----Via TARCH the architecture the compiler generates code for can be overridden. The value depends on the chosen compiler.
VERIFICATIONon, offoffTurn verification on/off.
VTK_OUTPUTon, offoffEnable/Disable VTK file output.
-
-
-
-

3   Invocation

-

Running the binary will print among the GPL licence header a line like the following:

-
-LBM Benchmark Kernels 0.1, compiled Jul  5 2017 21:59:22, type: verification
-
-

if verfication was enabled during compilation or

-
-LBM Benchmark Kernels 0.1, compiled Jul  5 2017 21:59:22, type: benchmark
-
-

if verfication was disabled during compilation.

-
-

3.1   Command Line Parameters

-

Running the binary with -h list all available parameters:

-
-Usage:
-./lbmbenchk -list
-./lbmbenchk
-    [-dims XxYyZ] [-geometry box|channel|pipe|blocks[-<block size>]] [-iterations <iterations>] [-lattice-dump-ascii]
-    [-rho-in <density>] [-rho-out <density] [-omega <omega>] [-kernel <kernel>]
-    [-periodic-x]
-    [-t <number of threads>]
-    [-pin core{,core}*]
-    [-verify]
-    -- <kernel specific parameters>
-
--list           List available kernels.
-
--dims XxYxZ     Specify geometry dimensions.
-
--geometry blocks-<block size>
-                Geometetry with blocks of size <block size> regularily layout out.
-
-

If an option is specified multiple times the last one overrides previous ones. -This holds also true for -verify which sets geometry dimensions, -iterations, etc, which can afterward be override, e.g.:

-
-$ bin/lbmbenchk-linux-intel-release -verfiy -dims 32x32x32
-
-

Kernel specific parameters can be obtained via selecting the specific kernel -and passing -h as parameter:

-
-$ bin/lbmbenchk-linux-intel-release -kernel kernel-name -- -h
-...
-Kernel parameters:
-[-blk <n>] [-blk-[xyz] <n>]
-
-

A list of all available kernels can be obtained via -list:

-
-$ ../bin/lbmbenchk-linux-gcc-debug -list
-Lattice Boltzmann Benchmark Kernels (LbmBenchKernels) Copyright (C) 2016, 2017 LSS, RRZE
-This program comes with ABSOLUTELY NO WARRANTY; for details see LICENSE.
-This is free software, and you are welcome to redistribute it under certain conditions.
-
-LBM Benchmark Kernels 0.1, compiled Jul  5 2017 21:59:22, type: verification
-Available kernels to benchmark:
-   list-aa-pv-soa
-   list-aa-ria-soa
-   list-aa-soa
-   list-aa-aos
-   list-pull-split-nt-1s-soa
-   list-pull-split-nt-2s-soa
-   list-push-soa
-   list-push-aos
-   list-pull-soa
-   list-pull-aos
-   push-soa
-   push-aos
-   pull-soa
-   pull-aos
-   blk-push-soa
-   blk-push-aos
-   blk-pull-soa
-   blk-pull-aos
-
-
-
-

3.2   Kernels

-

The following list shortly describes available kernels:

-
    -
  • push-soa/push-aos/pull-soa/pull-aos: -Unoptimized kernels (but stream/collide are already fused) using two grids as -source and destination. Implement push/pull semantics as well structure of -arrays (soa) or array of structures (aos) layout.
    • -
  • blk-push-soa/blk-push-aos/blk-pull-soa/blk-pull-aos: -The same as the unoptimized kernels without the blk prefix, except that they support -spatial blocking, i.e. loop blocking of the three loops used to iterate over -the lattice. Here manual work sharing for OpenMP is used.
    • -
  • list-push-soa/list-push-aos/list-pull-soa/list-pull-aos: -The same as the unoptimized kernels without the list prefix, but for indirect addressing. -Here only a 1D vector of is used to store the fluid nodes, omitting the -obstacles. An adjacency list is used to recover the neighborhood associations.
    • -
  • list-pull-split-nt-1s-soa/list-pull-split-nt-2s-soa: -Optimized variant of list-pull-soa. Chunks of the lattice are processed as -once. Postcollision values are written back via nontemporal stores in 18 (1s) -or 9 (2s) loops.
    • -
  • list-aa-aos/list-aa-soa: -Unoptimized implementation of the AA pattern for the 1D vector with adjacency -list. Supported are array of structures (aos) and structure of arrays (soa) -data layout is supported.
    • -
  • list-aa-ria-soa: -Implementation of AA pattern with intrinsics for the 1D vector with adjacency -list. Furthermore it contains a vectorized even time step and run length -coding to reduce the loop balance of the odd time step.
    • -
  • list-aa-pv-soa: -All optimizations of list-aa-ria-soa. Additional with partial vectorization -of the odd time step.
    • -
-

Note that all array of structures (aos) kernels might require blocking -(depending on the domain size) to reach the performance of their structure of -arrays (soa) counter parts.

-

The following table summarizes the properties of the kernels. Here D means -direct addressing, i.e. full array, I means indirect addressing, i.e. 1D -vector with adjacency list, x means supported, whereas -- means unsupported. -The loop balance B_l is computed for D3Q19 model with double precision floating -point for PDFs (8 byte) and 4 byte integers for the index (adjacency list). -As list-aa-ria-soa and list-aa-pv-soa support run length coding their effective -loop balance depends on the geometry. The effective loop balance is printed -during each run.

- --------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
kernel nameprop. stepdata layoutaddr.parallelblockingB_l [B/FLUP]
push-soaOSSoADx--456
push-aosOSAoSDx--456
pull-soaOSSoADx--456
pull-aosOSAoSDx--456
blk-push-soaOSSoADxx456
blk-push-aosOSAoSDxx456
blk-pull-soaOSSoADxx456
blk-pull-aosOSAoSDxx456
list-push-soaOSSoAIxx528
list-push-aosOSAoSIxx528
list-pull-soaOSSoAIxx528
list-pull-aosOSAoSIxx528
list-pull-split-nt-1sOSSoAIxx376
list-pull-split-nt-2sOSSoAIxx376
list-aa-soaAASoAIxx340
list-aa-aosAAAoSIxx340
list-aa-ria-soaAASoAIxx304-342
list-aa-pv-soaAASoAIxx304-342
-
-
-
-

4   Benchmarking

-

Correct benchmarking is a nontrivial task. Whenever benchmark results should be -created make sure the binary was compiled with:

- -
-

4.1   Intel Compiler

-

For the Intel compiler one can specify depending on the target ISA extension:

-
    -
  • AVX: TARCH=-xAVX
    • -
  • AVX2 and FMA: TARCH=-xCORE-AVX2,-fma
    • -
  • AVX512: TARCH=-xCORE-AVX512
    • -
  • KNL: TARCH=-xMIC-AVX512
    • -
-

Compiling for an architecture supporting AVX (Sandy Bridge, Ivy Bridge):

-
-make ISA=avx TARCH=-xAVX
-
-

Compiling for an architecture supporting AVX2 (Haswell, Broadwell):

-
-make ISA=avx TARCH=-xCORE-AVX2,-fma
-
-

WARNING: ISA is here still set to avx as currently we have the FMA intrinsics not -implemented. This might change in the future.

-

Compiling for an architecture supporting AVX-512 (Skylake):

-
-make ISA=avx TARCH=-xCORE-AVX512
-
-

WARNING: ISA is here still set to avx as currently we have no implementation for the -AVX512 intrinsics. This might change in the future.

-
-
-

4.2   Pinning

-

During benchmarking pinning should be used via the -pin parameter. Running -a benchmark with 10 threads and pin them to the first 10 cores works like

-
-$ bin/lbmbenchk-linux-intel-release ... -t 10 -pin $(seq -s , 0 9)
-
-
-
-

4.3   General Remarks

-

Things the binary does nor check or control:

-
    -
  • transparent huge pages: when allocating memory small 4 KiB pages might be -replaced with larger ones. This is in general a good thing, but if this is -really the case, depends on the system settings (check e.g. the status of -/sys/kernel/mm/transparent_hugepage/enabled). -Currently madvise(MADV_HUGEPAGE) is used for allocations which are aligned to -a 4 KiB page, which should be the case for the lattices. -This should result in huge pages except THP is disabled on the machine. -(NOTE: madvise() is used if HAVE_HUGE_PAGES is defined, which is currently -hard coded defined in Memory.c).
    • -
  • CPU/core frequency: For reproducible results the frequency of all cores -should be fixed.
    • -
  • NUMA placement policy: The benchmark assumes a first touch policy, which -means the memory will be placed at the NUMA domain the touching core is -associated with. If a different policy is in place or the NUMA domain to be -used is already full memory might be allocated in a remote domain. Accesses -to remote domains typically have a higher latency and lower bandwidth.
    • -
  • System load: interference with other application, especially on desktop -systems should be avoided.
    • -
  • Padding: For SoA based kernels the number of (fluid) nodes is automatically -adjusted so that no cache or TLB thrashing should occur. The parameters are -optimized for current Intel based systems. For more details look into the -padding section.
    • -
  • CPU dispatcher function: the compiler might add different versions of a -function for different ISA extensions. Make sure the code you might think is -executed is actually the code which is executed.
    • -
-
-
-

4.4   Padding

-

With correct padding cache and TLB thrashing can be avoided. Therefore the -number of (fluid) nodes used in the data layout is artificially increased.

-

Currently automatic padding is active for kernels which support it. It can be -controlled via the kernel parameter (i.e. parameter after the --) --pad. Supported values are auto (default), no (to disable padding), -or a manual padding.

-

Automatic padding tries to avoid cache and TLB thrashing and pads for a 32 -entry (huge pages) TLB with 8 sets and a 512 set (L2) cache. This reflects the -parameters of current Intel based processors.

-

Manual padding is done via a padding string and has the format -mod_1+offset_1(,mod_n+offset_n), which specifies numbers of bytes. -SoA data layouts can exhibit TLB thrashing. Therefore we want to distribute the -19 pages with one lattice (36 with two lattices) we are concurrently accessing -over as much sets in the TLB as possible. -This is controlled by the distance between the accessed pages, which is the -number of (fluid) nodes in between them and can be adjusted by adding further -(fluid) nodes. -We want the distance d (in bytes) between two accessed pages to be e.g. -d % (PAGE_SIZE * TLB_SETS) = PAGE_SIZE. -This would distribute the pages evenly over the sets. Hereby PAGE_SIZE * TLB_SETS -would be our mod_1 and PAGE_SIZE (after the =) our offset_1. -Measurements show that with only a quarter of half of a page size as offset -higher performance is achieved, which is done by automatic padding. -On top of this padding more paddings can be added. They are just added to the -padding string and are separated by commas.

-

A zero modulus in the padding string has a special meaning. Here the -corresponding offset is just added to the number of nodes. A padding string -like -pad 0+16 would at a static padding of two nodes (one node = 8 b).

-
-
-
-

5   Geometries

-

TODO: supported geometries: channel, pipe, blocks, fluid

-
-
-

6   Performance Results

-

The sections lists performance values measured on several machines for -different kernels and geometries. -The RFM column denotes the expected performance as predicted by the -Roofline performance model [williams-2008]. -For performance prediction of each kernel a memory bandwidth benchmark is used -which mimics the kernels memory access pattern and the kernel's loop balance -(see [kernels] for details).

-
-

6.1   Haswell, Intel Xeon E5-2695 v3

-
    -
  • Haswell architecture, AVX2, FMA
    • -
  • 14 cores, 2,3 GHz
    • -
  • 2 x 7 cores in cluster-on-die (CoD) mode enabled
    • -
  • SMT enabled
    • -
-

memory bandwidth:

-
    -
  • copy-19 47.3 GB/s
    • -
  • copy-19-nt-sl 47.1 GB/s
    • -
  • update-19 44.0 GB/s
    • -
-

geometry dimensions: 500x100x100

- --------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
kernelpipeblocks-2blocks-4blocks-6blocks-8blocks-10blocks-15blocks-16blocks-20blocks-25blocks-32RFM
blk-push-aos58.8249.8557.3459.9061.3762.1765.3064.0067.5464.4669.69104
blk-push-soa32.3233.4634.0234.6435.0635.0436.3135.4437.2035.1437.95104
blk-pull-aos56.9751.4156.0957.9259.9859.8363.3761.5565.5063.1167.02104
blk-pull-soa49.2946.2347.5051.9751.2749.5255.2353.1354.5049.7957.90104
aa-aos91.3566.1476.8084.7683.6391.3693.4692.6293.9192.2592.93145
aa-soa75.5165.6870.9471.3673.8375.4674.8479.4883.2877.7082.72145
aa-vec-soa93.8583.4491.5893.9694.3596.62101.7696.72106.37102.60110.28145
list-push-aos80.2980.9780.9581.1081.3782.4481.7781.4980.7281.9380.9383
list-push-soa47.5242.6545.2846.6443.4640.5944.9446.5541.5345.9844.8683
list-pull-aos85.3082.9786.4383.4286.3383.7086.4383.7783.1085.8984.4483
list-pull-soa62.1263.6163.2861.3266.7262.6564.8260.4958.0164.4662.5283
list-pull-split-nt-1s-soa121.35113.77115.29113.54117.00116.46114.78114.54110.83112.67117.85125
list-pull-split-nt-2s-soa118.09110.48112.55113.18113.44111.85109.27114.41110.28111.78113.74125
list-aa-aos121.28118.63119.00118.50121.99119.11118.83121.47121.62126.18120.12129
list-aa-soa126.34116.90129.45127.12129.41121.42126.19126.76126.70124.40125.22129
list-aa-ria-soa133.68121.82126.04128.46131.15132.25128.78133.50126.69124.40130.37145
list-aa-pv-soa146.22124.39130.73136.29137.61131.21138.65138.78127.02132.40138.37145
-
-
-

6.2   Broadwell, Intel Xeon E5-2630 v4

-
    -
  • Broadwell architecture, AVX2, FMA
    • -
  • 10 cores, 2.2 GHz
    • -
  • SMT disabled
    • -
-

memory bandwidth:

-
    -
  • copy-19 48.0 GB/s
    • -
  • copy-nt-sl-19 48.2 GB/s
    • -
  • update-19 51.1 GB/s
    • -
-

geometry dimensions: 500x100x100

- --------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
kernelpipeblocks-2blocks-4blocks-6blocks-8blocks-10blocks-15blocks-16blocks-20blocks-25blocks-32RFM
blk-push-aos55.7547.6254.5757.1058.4959.0061.7260.5664.0561.1066.03105
blk-push-soa30.0631.0932.1332.5432.7432.7233.8133.1934.9033.2135.75105
blk-pull-aos53.8048.6153.0854.9956.0856.6859.2058.1261.4958.7163.45105
blk-pull-soa46.9646.6148.8449.7050.3350.4652.3651.3954.2051.6155.71105
aa-aos91.4066.9978.4783.3886.6288.6292.9891.5497.0894.9398.90168
aa-soa83.0169.9675.8577.7279.0179.2982.3880.1185.7083.9187.69168
aa-vec-soa112.0396.52105.32109.76112.55113.82120.55118.37126.30121.37131.94168
list-push-aos75.1374.1875.2075.4275.2475.9975.8075.8075.5476.2276.2197
list-push-soa40.9938.1439.0038.8938.8939.6739.8739.2839.3540.0840.1397
list-pull-aos82.0782.8883.2983.0983.3283.4982.8282.8883.3282.6082.9397
list-pull-soa62.0760.4061.8961.3962.4360.9060.4862.8062.5061.1060.3897
list-pull-split-nt-1s-soa125.81120.60121.96122.34122.86123.53123.64123.67125.94124.09123.69128
list-pull-split-nt-2s-soa122.79117.16118.86119.16119.56119.99120.01120.03122.64120.57120.39128
list-aa-aos128.13127.41129.31129.07129.79129.63129.67129.94129.12128.41129.72150
list-aa-soa141.60139.78141.58142.16141.94141.31142.37142.25142.43141.40142.26150
list-aa-ria-soa141.82134.88140.15140.72141.67140.51141.18141.29142.97141.94143.25168
list-aa-pv-soa164.79140.95159.24161.78162.40163.04164.69164.38165.11165.75166.09168
-
-
-

6.3   Skylake, Intel Xeon Gold 6148

-
    -
  • Skylake architecture, AVX2, FMA, AVX512
    • -
  • 20 cores, 2.4 GHz
    • -
  • SMT enabled
    • -
-

memory bandwidth:

-
    -
  • copy-19 89.7 GB/s
    • -
  • copy-19-nt-sl 92.4 GB/s
    • -
  • update-19 93.6 GB/s
    • -
-

geometry dimensions: 500x100x100

- --------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
kernelpipeblocks-2blocks-4blocks-6blocks-8blocks-10blocks-15blocks-16blocks-20blocks-25blocks-32RFM
blk-push-aos113.0193.99108.98114.65117.87119.47124.95122.46129.29123.87133.01197
blk-push-soa100.2198.87103.63105.56107.02107.27111.61109.83116.16110.51110.29197
blk-pull-aos118.45102.54114.12117.82122.69124.31130.58127.85135.72129.65139.94197
blk-pull-soa82.6083.3687.1388.3988.8488.9692.4890.9395.7991.9298.64197
aa-aos171.32125.43147.73157.70163.35167.25175.39174.20182.54173.67187.76308
aa-soa180.85152.39165.84152.59171.90175.76184.94182.34189.43180.30193.54308
aa-vec-soa208.03181.51195.86203.41209.08212.34224.05219.49234.31225.92245.22308
list-push-aos158.81164.67162.93163.05165.22164.31164.66160.78164.07165.19164.06177
list-push-soa134.60110.44110.17132.01132.95133.46134.37134.33135.12134.91137.87177
list-pull-aos169.61170.03170.89170.90171.20171.60172.09171.95169.48172.08171.02177
list-pull-soa120.50116.73118.62118.00120.99118.15117.17121.41120.83120.00118.74177
list-pull-split-nt-1s-soa225.59224.18225.10226.34226.01230.37227.50228.42227.39231.65227.35246
list-pull-split-nt-2s-soa219.20214.63217.61218.13219.07221.01219.88220.09220.62221.68220.58246
list-aa-aos241.39239.27239.53242.56242.46243.00242.91242.46241.24242.96241.52275
list-aa-soa273.73268.49268.48271.79275.29274.56277.18272.67274.21275.24278.21275
list-aa-ria-soa288.42261.89273.26284.84283.88288.29290.72289.81293.36290.75292.93308
list-aa-pv-soa303.35267.21289.18294.96294.36298.16300.45301.71302.37302.88304.46308
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7   Licence

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The Lattice Boltzmann Benchmark Kernels are licensed under GPLv3.

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8   Acknowledgements

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This work was funded by BMBF, grant no. 01IH15003A (project SKAMPY).

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This work was funded by KONWHIR project OMI4PAPS.

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9   Bibliography

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[ginzburg-2008]I. Ginzburg, F. Verhaeghe, and D. d'Humières. -Two-relaxation-time lattice Boltzmann scheme: About parametrization, velocity, pressure and mixed boundary conditions. -Commun. Comput. Phys., 3(2):427-478, 2008.
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[williams-2008]S. Williams, A. Waterman, and D. Patterson. -Roofline: an insightful visual performance model for multicore architectures. -Commun. ACM, 52(4):65-76, Apr 2009. doi:10.1145/1498765.1498785
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Document was generated at 2017-11-21 15:43.

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